DSS 3

Mike Rosing

February 29, 2000

 

            DSS 3 is composed of several different microprocessors which create a complex system.  It is very different from DSS 2 which consisted of independent cards each with hard wired capabilities.  Each processor in DSS 3 is reprogrammable, so even though DSS 3 is still hardwired between components, the operations are very flexible.

 

            The main features of DSS 3 are:

 

·        32 channels of TTL input at 1 MHz sample rate

·        32 channels of TTL output at 1 MHz sample rate

·        8 individually programmable rate generators

·        2  25 bit DAC's at 1 MHz sample rate

·        2 16 bit DAC's at 200kHz sample rate

·        2 16 bit ADC's at 250kHz sample rate

·        runs under Windows NT (now called Windows 2000)

 

            The overall system is shown in figure 1.  The three visible main components include an Intel based PC running windows NT operating system, a large box holding input and output channels and a small rack mountable box containing analog output.  To give each of these a name for later reference, let’s call the PC the “Host”, the large box “Digital Interconnect” and the small box “analog output”.  Figures 2 through 15 show photos of the completed prototype.

 

            Inside the host are two ISA cards.  One is called the “PC44” and the other is called “PC32”.  The PC44 card is a full length board and contains two 16 bit analog to digital converters, two 16 bit digital to analog converters and a TMS320C44 Digital Signal Processor.  An adapter card is attached to this board which sends signals to the analog output box and gets signals from the digital interconnect box.  See figure 15.

 

            The PC32 card is a half length card which holds a TMS320C32 Digital Signal Processor and an adapter card.  There are analog and digital converters on the card, but they have never been used.  The adapter card attached to the PC32 drives signals directly to and from the digital interconnect box.  See figure 14.

 

            The digital interconnect box contains 3 cards and a front panel.  The front panel has three groups of 32 BNC’s, an input group, an output group, and the rate generator - PC44 interconnect group.  The LED driver card flashes an LED every time a signal on the front panel changes.  Its only purpose is instantaneous feed back that something is happening at a BNC connection.  See figures 6 - 8.

 

            The I/O Driver card buffers the input and output blocks for the PC32 adapter card.  The first 24 inputs are edge triggered and the last 8 are straight level readings.  All voltages in and around the digital interconnect box are 5V TTL.  See figure 9.

 

            The Rate Generator card contains nine processors.  One is a PIC microcontroller which interfaces to the PC32 and the other 8 are Motorola 56004 Digital Signal Processors.  Each processor creates an independent rate for use around the rest of the system.  See figure 10.

 

            The analog output box contains a 25 bit Digital to Analog Converter, a 127 dB attenuator (same as in DSS 2) and a 1 Watt audio amplifier capable of driving the 50 ohm attenuator.  See figures 2 - 5.

 

 

Figure 1: Overall System view

Digital Interconnect

 
 

 


Hardware Components Design

 

            DSS 3 has gone through several years of change.  The original plan was to use only the PC44 and PC32 cards and some interface cables.  When this failed to deliver adequate results, external cards were designed to give more capability.  The present system reflects this hardware learning process.

 

            The software controlling all the processors has gone through even more change.  Every single processor has seen its software rewritten at least three times, and for the PC44 and PC32 it is more like 10 times.  Some of this is due to hardware changes, but most is from change in philosophy.  By increasing response time to input a more complex system can be developed.  Many such tradeoffs were explored.

 

            Although the system is infinitely flexible, the following design philosophy has been found to work as well as DSS 2 in most cases.  The Windows NT operating system was chosen because it is very easy to get development tools.  While it has proven very useful for creating software over the entire system, its main drawback is that it is not a real-time OS.  This has limited some of the expected thruput of the system.

 

            The PC32 provides the system time base.  It has the fastest crystal in the system running at 64 MHz.  This clock determines the timing of everything.  All inputs are referenced to this clock and all outputs are changed according to this clock.  The rate generators are derived from this clock as well via a phased locked loop.  So while there may be skew across the system, the time delay is constant.

 

            The PC32 directly drives the 32 outputs via a code section called the “sequencer”.  Each bit of output can be changed once a microsecond, so the maximum frequency is 500 kHz.  Usually most sequence bits are flipped in 10’s of milliseconds so the precision is quite good.  The host downloads the sequence table to the PC32 and then tells the PC32 to run the sequence.

 

            The inputs are also checked once a microsecond.  This data collection is called the “UET” or Unit Event Timer.  All 32 bits are checked simultaneously, if a change is detected the input bits are time stamped and stored into internal PC32 memory.  The data is transferred to the host processor via interrupt control.  The PC32 buffer is capable of storing over 50,000 events, so even NT can keep up with several kilohertz input rates with no loss of data.  The sequencer and UET are intertwined at the microsecond level.

 

            The PC32 also controls the Rate Generator board.  A set of commands are sent from the PC32 to the PIC processor.  These commands are interpreted by the PIC to control each individual rate generator processor.  There are commands sent between the PIC and each rate generator so error detection and recovery are possible at the Host level.  External BNC’s connect lines between the Digital Interconnect box and each rate generator.  This allows the sequencer to control each individual rate generator (or anything else) and makes the entire system phase locked to one clock.  Each rate generator can be started by any external signal as well as the by

the sequencer.  Since each rate generator clock is derived from the PC32 master clock, any asyncronous start will still result in a phase locked output.

 

            The PC44’s main task is signal generation.  Several versions of software have gone from computing a sinusoidal waveform to simply outputting a raw data file.  The PC44 also collects raw data from its analog to digital converters.  This data is fed directly to the Host computer using interrupts.  The maximum output data rate is 1 MHz and the maximum input rate is 250 kHz.  The output rate is allowed for two independent DAC’s and the input assumes the ADC’s are sampled simultaneously.

 

            The adapter card attached to the PC44 is designed to send 25 bits to 8 different devices or to collect a maximum of 25 bits from 8 different devices.  The analog output box is attached directly to the adapter card.  At the present time only output data is written to the Analog Output box.  This includes 25 bit DAC data and the 7 bit attenuator setting.

 

            There is also a connection from the Digital Interconnect box to the PC44 adapter card.  These lines connect to the three external interrupts connected to the TMS320C44 processor and to data lines for input.  These input lines are called “gates” and are used to turn PC44 activity on and off.

 

            The C44 processor actually has 4 interrupt lines, but only three are brought to the outside world.  The interrupts are programmed to drive the DMA controller in the C44 processor.  One interrupt is used for both Analog to Digital converters and the other two interrupts are connected to each Digital to Analog output channel.

 

System Design

 

            The overall data flow of the system is from Host to PC32, Host to PC44 and then the PC44 and PC32 dump data into the Host.  The Host boots the PC32, downloads the sequencer/UET program and then downloads the sequence data.  The Host then boots the PC44 and downloads its software and associated data.  The Host sends commands and data to the PC32 that set up the rate generators which will be used to run the PC44.

 

            Once everything is set up, the Host tells the PC32 to “go”.  The sequencer starts running and bits are flipped on the output BNC’s.  These are connected via the front panel to the rate generator inputs including their “start” and “stop” bits.  Some are connected to the PC44 gate bits.  The rate generator outputs are connected via the front panel BNC’s to the PC44’s interrupts.

 

            On every interrupt the PC44 moves data, either from memory to a DAC or from an ADC to memory.  The latter case is complicated and uses two interrupt channels inside the C44 processor to start the conversion and then move the data.  It reads both 16 bit analog to digital converters at the same time and stores the data as one 32 bit word.

 

            The design principle of the front panel is to allow any possible input to start or stop any activity.  While the sequencer is designed to do everything in an “open loop” fashion, it is possible to connect other signals from any source to any input.  This creates many possibilities for interactive control.

 

            The 8 level sensitive input latches can be used to monitor any external activity.  The Host can read the state of these lines to determine if the sequencer has finished or if the ADC gate is off.  For time scales in the 100 millisecond range the Host can easily detect and respond to these inputs.  The exact time of each change will be stored in the PC32 data.

 

Component Details: PC32

 

            The following details may not mean much to most users of DSS 3.  The purpose is an overview of each component so some comprehension of the complexity can be appreciated.  If changes in hardware or software are requested, accomodation is certainly possible.  It just takes a bit of time.

 

The PC32 card has a 96 pin DIN connector which gives access to the processor’s address and data bus as well as many control signals.  Attaching external components to this connector has proved difficult.  By using CPLD’s (Complex Programmable Logic Devices) and placing them close to the connector many noise problems were eliminated.  The adapter card connected to the PC32 contains two CPLD’s.  One is used as an address decoder and the other is used as a 32 bit data bus driver.  The CPLD’s are programmed using a Xilinx IDE, which can be found on the “geraldo” computer in MEL.

 

            The address decode section converts specific addresses into individual select lines.  Some of these lines are sent to the PIC processor on the Rate Generator board and are used for reset and handshake commands.  Two select lines are sent to the buffer driver CPLD to enable reading or writing from the processor bus.

 

            The buffer driver CPLD is very simple, but at 32 bits wide it uses most of the I/O lines available on the chip.   This bus driver allows very long cables (up to 3 meters) to be used to connect the Digital Interconnect box with the PC32 processor.

 

            The schematics for the adapter card and each CPLD can be found in the DSS 3 notebook as well as on the computer called “geraldo” in the Medical Electronics Lab..  The PC0 interrupt line from the ISA bus has been directly wired to external interrupt 3 on the C32 processor because the header connect did not work.  (Decodes0 on the 96 pin header also did not work, so the address decode CPLD fixes this.)

 

Component Details: PC44

 

            The PC44 card has an 80 pin header which connects the processor’s address and data bus to the outside world.  The adapter card connected to the PC44 is similar to the PC32 card in that it has an address decode CPLD and a bus driver CPLD.  For the PC44, there are 8 output devices assumed available and 8 input devices assumed available.  The bus driver chip reads or writes from any of these devices.

 

            A small 16 pin header is also attached to the PC44 adapter card.  This connector brings over the interrupt and gate lines from the Digital Interconnect front panel.  The gates are directly connected to data lines starting at D16.  This choice is historic - the original gates were input directly on the I/O connector of the PC44 card.  This third interrupt is not directly accessible on the 80 pin header, so a wire is attached from pin 78 of this header to the EXT_INT2 line of the PC44 Digital I/O connector.  Because the I/O connector was 50 pins wide, there is an adapter that converts 50 pins to the 16 pin header (see figure 13 near the bottom).

 

            A wire is attached between the A_TCLK0 and EXT_INT2 on the PC44’s digital I/O connector.  This allows the timer to send a signal to the DMA controller which in turn tells the ADC to start a conversion.  The interrupt is activated on the opposite edge of the same clock and then reads the ADC value and stores it in memory.  By using the DMA controller to collect and store analog input data the PC44 processor can easily monitor the gate signals for each channel and deal with Host commands in the one microsecond time scale demanded by the sequencer.

 

            Descriptions of the C44  (and C32) processors can be found in their respective hardware manuals.  Descriptions of the PC44 and PC32 cards can be found in their respective manuals as well.  All these manuals can be found in the Medical Electronics Lab office (on my desk).

 

Component Details: Digital Interconnect

 

            The Digital Interconnect box is large and at first glance confusing.  The front panel has 96 BNC’s each with its own LED.  The original idea was to make the LED’s indicate the level on each BNC, but it took more CPLD’s than I cared for.  At present the LED’s flash at about 10 Hz if there any changing voltages on the line.  This has proven a good indicator when things are dead - none of the lights flash.

 

            The front panel is grouped in three blocks of 32 BNC’s each.  The top group are inputs, the middle group are outputs and the bottom group contain the rate generators and PC44 interrupts and gate connectors.  Each group of 32 is connected to one CPLD on the LED driver board.

 

            All the CPLD’s are programmed with the same schematic.  A slow clock is created with an LM555 timer chip.  This clock drives all the CPLD’s, so all the LED’s on the front panel will change state at the same time.  If the frequency on the BNC is slower than 10 Hz, the actual change in voltage will be directly observed.  If the change is faster than 10 Hz, then only the 10 Hz slow clock frequency will be visible.  Schematics are in the DSS 3 notebook.

 

            Connectors go from the LED panel to the I/O driver, Rate Generator and PC44.  This is the main interface of all digital signals in the system.  For example, it is very easy to connect any rate generator to any PC44 interrupt.  It is also very easy to get confused, so care should be taken when making connections so that the software and hardware work properly together.  There are 8 BNC's per row, and being off by 1 is a common error because numbering begins at 0.  By mapping the hardware BNC's as bits in bytes, errors between hardware and software can easily be corrected.

 

            The I/O driver card isolates the input and output data lines and allows a single set of 32 lines to be read or written by the PC32.  The output data lines are latches, once set they will hold their voltage of high or low until another write from the sequencer occurs.  One CPLD contains all 32 latches which are connected to the front panel via the LED driver board.

 

            The input latch CPLD contains 24 edge sensitive latches and 8 level sensitive buffer drivers.  The edge sensitive latches require a “clear” signal which is created by a 74123 one shot.  As soon as the PC32 reads the latch (about once every 1300 nanoseconds with the present software), the IOSREAD signal fires the one shot which clears the inputs.  Since the read and clear signals are asynchronous with the data signal, the circuit does not allow a clear to occur if a data line has not already been set and read.  The circuit for the input latch can be found in the INPUT_32 CPLD schematic.

 

            The output latch CPLD is simply a 32 bit D flip flop with a single strobe (called IOSWRITE).  The CPLD is capable of driving 24 ma on each output pin.

 

            The main problem encountered with the board has been the clock speed.  Even with the outputs set to “slow slew rate”, the rise and fall edges are measured at 10 to 15 nanoseconds which is too fast and generates too much noise.  Originally, the inputs were filtered identically as in DSS 2.  This proved to be a major problem because it generated multiple input signals, especially on a falling edge.  Removing the filter bank eliminated the problems.  While more testing should be done, it appears that all samples are now clocked correctly.

 

            The Rate Generator board is definitely the most complex circuit in the entire system.  The present design was derived from two previous boards which had poor reliability.  The present board has 8 rate generators.  In the prototype 7 work but only 3 are essential for the operation of DSS 3.

 

            There are three major components on the Rate Generator card.  The connection to the PC32 goes into a PIC16C74 microcontroller.  The PC32 sends commands to reset, boot and setup the rate generator parameters of any one of the rate generators.  The PIC uses the rate generator number as select lines into the CPLD.  The CPLD switches the SPI serial lines from the PIC to the selected rate generator.  In essence, the CPLD is a one of 8 demultiplexor.  Each rate generator is a Motorola DSP56004 microprocessor.  The DSP’s core program is basically two instructions: add a constant to an accumulator and output the most significant bit.

 

            The output bits of each rate generator are latched by the CPLD.  This also acts as a buffer driver so the rate bits can be sent directly to the front panel of the Digital Interconnect box.

 

            Each rate generator has an external start and stop control line.  The start lines are connected to the DSP’s generic I/O line #3 and the stop lines are connected to the non-maskable interrupt input.  This latter signal is also a “mode” bit during the DSP’s boot process and it must be high when attempting to boot or the DSP will not run at all.

 

            The 56004 processor has two 56 bit accumulators.  Unfortunately, only the lower 48 can be used at the highest possible clock rate.  The master clock from the PC32 is divided down to 16 MHz and this is used directly by the PIC.  The DSP’s use their internal PLL’s (Phase Locked Loop) to build that backup to 64 MHz.  Because there are 2 clocks per instruction and 2 instructions per update, the sample rate of the rate generators is also 16 MHz.  With 48 bits of precision, this gives about 60 nanohertz.  To get some idea of what this means, if the last bit is set and all others are clear, starting the counter at zero and adding this one bit will take 248/16x106 seconds before the output changes from 0 to 1.  This is more than 200 days!

 

            The software which runs the PIC and DSP processors will be described later in the software section.  Schematics of the rate generator are in the notebook and on geraldo.

 

Component Details: Analog Output

 

            The Analog Output box consists of a backplane and two 24 volt power supplies.  The power supplies are set up as positive 24 and negative 24 to run the op amps.  Each card has voltage regulators to bring this voltage down to the required level.  This can be +/-5, +/-15 or

+/- 12 depending on the card.

 

            The card cage is a standard VME 3U rack mountable module with 64 pin DIN connectors.  There is room for a total of 8 different modules to be plugged in  The attenuator slot is twice as wide as the other slots.  Room is made for two complete channels of DAC, amplifier and attenuator as well as a pair of spare slots for either ADC's or filters.

 

            The 25 bit data bus and the read or write select lines are run across the bus along with power and ground.  Jumpers are mounted on each card to determine its address on the bus.  This basically selects any one of the write lines and connects it to the write strobe of a device.

 

            The 25 bit DAC has 4 regulators and one analog output on its card.  This device can accept  data at 1 MHz rates.

 

            The output of the DAC is connected to a power amp card.  This card only takes power off the backplane, it is purely an analog component.  The power amp is capable of driving the 50 ohm load of the attenuator and all following loads.  The power amp converts the +/- 10 volt signal from the DAC to a high current +/- 7 volt signal for the 50 ohm attenuator.  This ensures no more than 1 Watt is transmitted out the power amp (that allows 0.14 Amps to the speaker).

 

            The output of the power amp is fed to the attenuator.  This is the same attenuator used in the DSS 2.  The 7 data bits used to set the attenuator need to be moved up to the high word of the PC44 and inverted (when a control line is grounded it turns a relay on which enables attenuation).  The Host can send the PC44 a command at anytime to change this value.

 

Component Costs

 

            The component costs (in US dollars) break down as follows:

 

PC32 card with high speed clock and memory addons - 1150

PC44 card with high speed clock and memory addons - 8290

Digital Interconnect box ------------------------------------------ 7500

Analog Output box ------------------------------------------------ 7000

Windows NT Host ------------------------------------------------- 2000

 

Total cost to duplicate prototype ---------------------------$25,940

 

The Digital Interconnect box breaks down as 2000 per card and 1500 for the box.

The Analog Output box breaks down as 1500 DAC, 1000 attenuator and 1000 box, and 500 for the amplifier.

 

The vast majority of the costs for the Digitial Interconnect and Analog Output box are labor related.  These costs could be reduced by a factor of 2 or more if built by students or if the

cards are fabbed by professional prototype houses.  In the latter case making changes is far

more expensive than by using student labor.

 

            If the attenuator is not needed, the entire Analog Output box can be considered optional.  Otherwise, only the 25 bit DAC card is an option.  To use the system with ADC and DAC, the entire Digitial interconnect box is pretty much required.  The LED driver board is optional but some kind of board needs to connect the BNC's from the PC44 to the front panel.

 

DSS 3 Software

 

            The DSS 3 hardware is relatively straight forward.  The software side of things is far more complex.  In this document I only discuss software which communicates directly with the hardware.  A great deal of software sits at a higher level: computing sequencer data and analyzing ADC data are examples.

 

            The highest level software on the Host which is discussed here will be the user interface to the driver software.  This software connects user data and commands with the PC32 and PC44.  The software on these cards then interprets that data as its own sequence of commands.  The most complex chain is from the Host to a Rate Generator.

 

            Software drivers in Windows NT are a difficult undertaking.  To reduce this difficulty to a manageable level, a development suite called WinDK was purchased from Bluewater Systems.  The use of their subroutines and macros made driver writing tolerable.  The end result are the files PC32_driver.c and PC44_driver.c.  These routines must be compiled in a special WinNT environment called DDK.  The output files must then be moved to the system drivers directory.  In addition the registry must be set up to know that hardware has been added to the system.  Bluewater Systems manuals describe all the necessary steps in this process with additional help available from the WinNT OS itself.  When the system boots the drivers are automatically installed.

 

            The WinDK interface software sits on top of the drivers.  These are sets of subroutines which link user programs to the drivers.  The files are called PC32_windk.* and PC44_windk.* where * = c or h.  These subroutines call NT operating system standard calls which in turn call specific driver routines.

 

            The operating system fills in specific information which was created at boot time when the driver was originally loaded.  So what is really happening is that user software calls a WinDK subroutine, which calls the OS, which calls the driver, which calls the OS hardware interface.  Because this takes a lot of clock cycles and because the OS can preempt any non interrupting process, the actual time it takes between any two WinDK calls can vary from microseconds to milliseconds.  This is much faster than human response time in all cases, but it still limits thruput.

 

            The software running on the PC44 and PC32 was developed using tools including a hardware debugger and software IDE (Integrated Development Environment).  The hardware debugger bypasses the ISA bus and goes straight to the core of the processor allowing all registers and memory to be examined.  It also allows single-stepping any instructions as well as the ability to run the processor at full speed and then break at a given memory access or location.

 

            Both the PC32 and PC44 are turned on in two stages.  The fist stage is called a boot process.  The PC32 boots from its onboard dual ported RAM which must first be loaded by the Host.  The PC44 boots from its on board flash ROM.

 

            The PC44 and PC32 processors are presently booted with a small program called “core”.  The task of core is to load the second stage program.  The core program has not changed in several years, but the main programs are constantly changing  Using this two stage boot process, the Host can change the software running in the PC44 or PC32 on the fly by sending a command which causes the main program to jump back to core.  It can of course simply reset the DSP’s and reboot them at any time as well.

 

            To load a program from the Host to DSP, the object file output from the TI assembler/linker is first read into Host memory.  The Host strips out the code and data sections and feeds them to the core routine indicating the destination address and size.  The core program works with the Host to transfer all the information and then jumps to the indicated starting address.

 

            Both the PC32 and PC44 core routines work in a similar way so the loading routines are almost identical.  The main difference is in the hardware: the PC32 has a 2kx16 bit dual ported RAM buffer and the PC44 has 4kx32 bit RAM.  While these differences are mostly seen in the driver level code, it does introduce some differences at the user level.  The files COFF.h, PC32_boot.c and PC44_boot.c call the subroutines in the *windk.c files and are used to boot up their respective processors as well as to load the main program.

 

            Communication between the Host and either DSP is via the on board dual ported RAM.  The Host uses a Write_Dualport() subroutine to send commands and data, then uses a Read_Dualport() subroutine to get the response.  Errors are easy to track and many error codes are used to diagnose problems.  How the DSP’s interpret the commands depends on the program which has been loaded into them.  This tight coupling requires user level programs to understand the data structures which the DSP’s demand.  Every time a DSP program is changed it forces changes at the user level as well.  So even though the system is very flexible it still takes a bit of time to successfully change anything.

 

            Several different methods of producing sine waves with the PC44 and its DAC hardware have been tried.  Attempting to compute the waveform on the fly proved far too slow and no interrupts from the Host could be tolerated.  Building the entire waveform in memory did work, but it limited the maximum play out time.  The latest version allows the Host to download a buffer of data and the PC44 replicates and plays it out.  This form allows any wave shape so long as the rise, fall and central loop blocks fit in 1 megaword of RAM.

 

            The PC44 will compute any of three envelopes on top of the buffer data.  These are linear, cosine and gaussian forms.  The Host tells the PC44 the rise type, the number of points in the rise, the fall type and the number of points in the fall.  The Host also tells the PC44 what the length of the buffer block is and the total number of points to be played out.  This latter value is a 64 bit number which allows many hours of playback of a single buffer.

 

            The PC44 then sets up the DMA controller to accept external interrupts.  The interrupts are enabled by the gate signals.  The number of points to be played out is all the PC44 knows, there is no time reference.  The time taken to play out a wave form is determined by the rate generator connected to the interrupt line.  It is the Host’s responsibility to ensure that the users requested play time and sample rate are correctly converted into a number of points for the PC44 to play.  The Host must also ensure that the gate signal is long enough to play the entire wave form (but can use the gate to turn off the signal if so desired).

 

            The ADC input is also controlled by a gate and interrupt line.  The ADC interrupt line is connected to the timer 0 clock input.  The timer is set up to generate an interrupt every time a falling edge occurs on the clock 0 input.  The interrupt is sent to the DMA 4 controller, which does a start conversion strobe using a read and then writes dummy data to a nonexistent address.  The rising edge of the ADC interrupt is directly fed to DMA 1 controller. This reads the ADC value and writes it directly to dual port RAM.

 

            The DMA controller is capable of resetting itself when it hits the end of a buffer.  By splitting the DMA 1 into two blocks, the C44 processor can see when half of RAM has been filled.  It sends an interrupt to the Host along with a counter telling the Host which block has filled.  The driver software in the Host is connected to the interrupt via the OS.  The Host driver moves the data from dual port RAM to its own internal buffers and updates its pointers.

 

            The Host driver is called when the OS decides to call it.  The delay time from when an interrupt occurs to when it is serviced can be quite long and there is no way of determining it.  We have set the interrupt to be highest priority but the time delay seems to be determined by the Host operating system rather than by a clock.  The entire process is open loop.  Failures can easily be seen if sample rates on the ADC exceed 250kHz.  At 300 kHz sample rates the data loss is consistent.  So even though the hardware is capable of collecting data at 500 kHz, the OS can not keep up with the interrupt rate needed to move the data from the PC44 to Host memory.  It is not clear that faster computers would help, but it is an experiment worth trying.

 

            The PC32 program also runs in several stages.  The first stage is command mode and the second stage is sequencer mode.  The command mode allows the Host to change or read any internal parameters in the PC32.  This includes downloading the sequencer data and “master loop” data.  Once the PC32 and rate generators have been set up, the Host sends a “go” command and the PC32 enters sequencer mode.

 

            The purpose of sequencer mode is to read the input lines and modify the output lines at a 1 MHz rate.  The present system is close to this goal taking about 1.3 microseconds per loop.  The master control data tells the sequencer how many times to cycle a block of data and how long the block is.  As many as 500 blocks can be cycled with up to 54,000 total steps in all the blocks.  This allows a great deal of output complexity at a megahertz rate.

 

            When events occur, the PC32 stores the input data along with a clock time.  The clock is an internal 32 bit timer based on the external 64 MHz clock.  It increments the counter once a microsecond.  When the PC32 receives the go command, the counter is cleared.  The counter can be cleared at any time while the sequencer is running, it is one of the few commands the sequencer will accept.

 

            As the sequencer runs it compares the relative elapsed time to the stored sequence time and outputs the associated bits when time is up.  It also monitors changes in the input data bits, ignoring when the 24 edge triggered bits go to zero.  When changes occur, the time stamp and 32 input bits are stored in a buffer.  Up to 55,0000 data points can be stored before an overflow occurs.

 

            The Host gets the input data by sending interrupts to the PC32 card.  Each interrupt is tied to the DMA controller which reads from the internal buffer and writes to dual port RAM.  This data transfer happens at the user level.  At present an independent thread is run to move UET data from the PC32 to permanent storage.  Data rates of 100kHz have been sustained with no errors, but it is unlikely that any real data would create rates higher than a few kilohertz.

 

            Another command from Host to PC is rate generator setup.  The PC32 clears the handshake lines and resets the PIC processor on the Rate Generator board.  It takes several hundred milliseconds for the PIC to wake up and initialize the Rate Generator board.  Once the PIC is awake it waits for commands from the PC32.

 

            Hardware handshaking is used to ensure good data transfer between PC32 and PIC.  When the Host sends data for a rate generator, the PIC is instructed to reset, boot and then download the data to the selected rate generator.  Any errors on the way are sent back to the Host.

 

            The PC32 can instruct a rate generator to free run which happens immediately after all its data is loaded, or to wait for external start.  In all cases, the Host must tell the PC32 to set up the output latches so the “start” bits are low and the “stop” bits are high.  The rate generator DSP’s will not boot otherwise.

 

            The PIC is programmed using a PROM burner.  Its program resides in internal ROM which is UV erasable.  The program was written using a simple text editor like Notepad and then assembled and linked using the MPLAB IDE.  While the present code was debugged without an emulator, the Medical Electronics Lab is now equipped with one.  This will make the job of making changes much easier.

 

            When the PC32 takes the PIC out of reset, the PIC initializes its I/O lines and waits for commands from the PC32.  The commands for any rate generator ( 0 <= x <= 7) are:

 

1 - reset x

2 - boot x

3 - download phase and count for x

4 - upload phase and count from x

5 - stop x

6 - start x

7 - external start x

 

            Resetting any rate generator only involves one bit in an I/O port.  Booting any rate generator is a complicated process.  The PIC sets up the CPLD to connect its serial lines to the correct rate generator, then releases the DSP’s reset line.  The DSP program is stored in PIC memory and sent over the serial lines.  This only works if the rate generator’s external stop line is held high because the stop line is connected to one of the DSP’s boot mode lines.

 

            After the program is sent, a block of zeros is sent to fill out the rest of the DSP’s internal RAM.  When full, the DSP jumps to the start of code and initializes its PLL, serial lines and external ports.  The DSP runs at 64 MHz internally which is 4 times its external clock.  The DSP then sends an acknowledge back to the PIC to tell it that it has booted properly.  If the PIC fails to see the ack, it reports an error to the PC32.

 

            The phase and count words are each 48 bits wide.  The phase is the initial value loaded into the output accumulator and the count is added to the output accumulator each cycle.  The cycle time is 16 MHz, so the highest possible frequency of the rate generator is 8 MHz.  With 48 bits, its resolution is 16x106 / 248 = 56.8 nanohertz.

 

            The rate generator can be controlled by the PC32 to free run, stop or be externally controlled.  By sending the correct command, the PC32 tells the PIC, which then tells the rate generator which mode to run in.  The hand shake between all processors is very good, so the Host can be very confident that a rate generator is operational if no errors are reported.

 

            The rate generator code is written using a text editor, then assembled and linked using Motorola DSP56K software.  The object code is then translated from S-record format to PIC data format for inclusion with the PIC ROM code.  Any changes in the rate generator are incorporated by reprogramming the PIC.  Testing is challenging but the rate generator code is simple so fixing bugs can be done with trial and error.

 

            The files for the DSP’s are rategen56.asm which is converted to rategen56.tbl and combined with the PIC’s rategen8.asm to create rategen8.hex.  This latter file is burned into the PIC and the PIC is placed on the rate generator board.  The 56k software resides on the computer called “bernice” in MEL.  A batch program will compile, link and generate the .tbl file.

 

            The output of each DSP is latched using the CPLD.  This acts as a bus driver as well, so the rate generator output is sent directly to the Digital Interconnect front panel.  Although programmed as “slow slew”, the CPLD output switches in about 10 nanoseconds.  While excellent for digital systems, interfacing to analog inputs has given rise to some problems.

 

Photos of third generation prototype DSS 3

 

            The following pictures show the prototype in a lab environment.

Figure 2:  Prototype in lab

 

 

Figure 3:  Front panel connections

Figure 4:  Typical prototype software

 

 

Figure 5: Analog Output box

Figure 6:  Digitial Interconnect front view

 

 

Figure 7:  Digital Interconnect close up

 

 

Figure 8:  Digital Interconnect side view

 

 

Figure 9: I/O Driver board

 

 

 

 

 

 

Figure 10: Rate Generator board

 

 

 

Figure 11:  LED Driver and front panel wiring

 

Figure 12:  LED driver close up

 

 

 

 

Figure 13:  PC44 and PC32 installed

 

Figure 14: PC44 with adapter card

 

 

 

 

Figure 15: PC32 with adapter card